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? semiconductor components industries, llc, 2000 november, 2000 rev. 1 1 publication order number: mc33567/d mc33567 dual linear controller for high current voltage regulation the mc33567 dual linear power supply controller is designed to facilitate power management for motherboard applications where reliable regulation of high current supply planes is required. it provides the drive, sense and control signals to interface two external, nchannel mosfets for regulating two different supply planes. undervoltage, short circuit detection places the operation of the system into a protected mode pending removal of the short. features ? mc335671: two, independent regulated supplies 1.515 v supply for gtl and agp planes 1.818 v supply for i/o plane and memory termination ? mc335672: dual 2.525 v supplies for clock and memory ? undervoltage detection and protection mode ? drive capability for sot223, dpak, and d 2 pak mosfets ? bypass function for 3.3 v agp card detection applications ? motherboards ? dual power supplies +3.3 v in shdn1 sns1 drv1 control gnd +12 v 3.3 v 66 k simplified functional block diagram v out1 8 4 3 2 1 startup & undervoltage shutdown ref +12 v v in bypass on uvlo ref +3.3 v in shdn2 sns2 drv2 control 3.3 v 66 k v out2 5 6 7 startup & undervoltage shutdown ref +12 v v in bypass on ref http://onsemi.com pin connections mc567x alyw 1 8 so8 d suffix case 751 marking diagram x = 1 or 2 a = assembly location l = wafer lot y = year w = work week 18 3 4 gate1 drv shutdown1 v cc 2 gate2 drv sense1 gnd shutdown2 sense2 see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information 7 6 5
mc33567 http://onsemi.com 2 maximum ratings* rating symbol value unit supply voltage v cc 12.5 vdc operating ambient temperature t a 0 to +80 c operating junction temperature t j 5 to +125 c lead temperature (soldering, 10 seconds) t l 300 c storage temperature range t stg 55 to +150 c package thermal resistance, junction to ambient r q ja note 1. 159 c/w thermal resistance, junction to case r q jc 28 c/w 1. minimum pad test board with 5 mil wide and 2.8 mil thick copper traces1 inch long. *all characterizing done with mtd3055vl nchannel mosfets. dc electrical characteristics characteristic symbol min typ max unit supply voltage v cc 9.0 12 12.5 v quiescent current i ql i qh 6.0 7.0 9.0 10 ma under voltage lockout undervoltage lockout uvlo 7.0 8.5 9.0 v hysteresis v hys 0.2 0.5 0.9 v drive drive voltage (gate to ground) v drv 10.5 v gate drive source output current (pin 1, pin 7) i pkdrv 10 20 30 ma gate drive sink current (steady state) i sink 5.0 7.0 10 ma shutdown shutdown threshold shdn 0.8 1.13 1.3 v shutdown hysteresis shdn hys 130 mv shutdown disable time shdn tdis 0.5 2.0 s shutdown current threshold i shdn 37 a short circuit short circuit response time sc td 250 s short circuit on time sc ton 0.5 0.8 1.5 ms short circuit off time sc toff 20 40 60 ms short circuit/undervoltage detect (load current increased until output drops) sc uvd 70 80 %vout output regulation mc335671 regulator 1 regulator 2 mc335672 v reg1 v reg2 1.818 1.515 2.525 v output voltage regulation (fullload to noload @ 2570 c) v reg% 2.5 +2.5 %
mc33567 http://onsemi.com 3 5 v v ref v ref v ref figure 1. functional block diagram ref out + a1 5 v fault logic fault shdn1 5 v uvlo fault reg 1.515 v sns2 off on drv2 v ref fault logic fault shdn2 5 v uvlo fault comp hys bypass on shdn1 out 5 v v ref glitch filter out in 5 v 5 v v ref 5 v glitch filter out in v ref v ref 75% out + a2 5 v in1 in2 in3 or * v ref uvlo uvlo 8 v cc 2 3 6 5 4 1 7 +3.3 v in q1 q2 1.515 v 1.818 v shdn1 sns1 sns2 shdn2 5 v reg 5 v v ref v fb v fb * internal ground disables bypass on function on the 1.818 v regulator in the mc335671 and on the 2.525 v regulators in the mc 335672. v ref reg 1.818 v sns1 off on drv1 in1 in2 in3 or drv2 drv1 5 v v ref comp hys bypass on shdn2 out a1 and a2 are undervoltage comparators. to sns1 to sns2 pin assignments and functions pin # pin name pin description 1 gate 1 drive drives mosfet into linear region. is internally clamped to ground in power down mode. 2 sense 1 line returns regulated output from mosfet. 3 shutdown 1 at ttl high level turns off regulation for gate 1. effectively grounds gate 1. (internal pullup to 3.3 v) 4 ground 5 shutdown 2 at ttl high level turns off regulation for gate 2. effectively grounds gate 2. (internal pullup to 3.3 v) 6 sense 2 line returns regulated output from mosfet. 7 gate 2 drive drives mosfet into linear region for 1.515 v operation. saturates external fet in bypass mode. is internally clamped to ground in power down mode. 8 12 volt input supply voltage for operation and gate drive output.
mc33567 http://onsemi.com 4 operating description the mc33567 dual linear controller is designed for power management applications where high current, voltage regulation is needed. some computer applications include: ? 1.515 v agp (advanced graphic port) and gtl+ (gunning transistor logic intel's electrical bus technology) ? 1.818 v i/o planes on motherboard ? 2.525 v clock and memory hiccup mode if the output drops below 75% of the regulated threshold for greater than 250 m s or a short circuit condition exists, that output will go into hiccup mode. this means that the output is turned on for 1.0 ms and off for 40 ms for a duty cycle of 1:40. please refer to figure 2. each transition from low to high of the input restarts the hiccup mode holdoff period. once the short circuit is removed or the output comes back to the regulated threshold, it will operate under normal operating conditions. 40 ms 1 ms figure 2. hiccup mode duty cycle shutdown the shutdown pin is connected to the external board (agp or gtl+). please refer to figure 3. figure 3. 1.5 v/3.3 v agp card detection pin 5 truth table pin 5 no connect = 1.515 v ldo drive out active pin 5 < 0.8v = shutdown (drive out 0 v) 1.3 v < pin 5 < 4.1 v = 1.515 v ldo drive out active pin 5 > 4.2 v = 3.3 v bypass mode (drive out = v in for fet) 1 2 3 4 8 7 6 5 1.8 v/1.5 v mc33567 gate 2 drv sense2 shutoff2 r7 10 k 12 vin 3.3 vin 3.3 vin agp card type detection agp card voltage 1.5 v / 3.3 v the way in which the external board is wired to the shutdown pin will determine the output of the mc33567. listed are the conditions the external board is wired and the corresponding output voltages: 1. if there is no connection on the external board, there is an open and the output will be the regulated output voltage. 2. if there is a ground on the external board which will cause the shutdown pin to be less than 0.8 v, the mosfet turns off and there is no output voltage. 3. if there is a resistor on the external board pulling the shutdown pin above 4.1 v, the output will be in the bypass mode. in this mode, the mosfet is fully on, or fully enhanced, and the output will be whatever voltage is supplied to the input voltage of the mosfet, v in . 4. if the shutdown pin is between 1.3 v and 4.1 v, the output will be the regulated voltage. tables 1 and 2 are the logic tables for the shutdown pins. note that the logic tables are not the same for the 1.515 v regulator and the 1.818 v regulator. the mc335672 does not have the fullon bypass feature. table 1. logic table for shutdown (pin 5) on the 1.515 v regulator shutdown pin 1.515 v regulator output no connect 1.515 v 0.8 v shutdown 1.3 v shdn 4.1 v 1.515 v 4.2 v v in = bypass table 2. logic table for shutdown (pin 3) on the 1.818 v regulator shutdown pin 1.818 v regulator output no connect 1.818 v 0.8 v shutdown 1.3 v 1.818 v
mc33567 http://onsemi.com 5 sense the sense pins provide tight regulation of the load voltages with varying load currents. when the load is located at a distance, there will be a voltage drop due to the resistance loss of the trace. if the load is not near the mc33567, it is recommended that the sense pins be used. connect the sense pins as close to the load as possible. use a separate trace to connect the source of the nchannel mosfet to the load. refer to figure 4. figure 4. sense v in 6 r l 7 capacitor selection stable operation is achieved by preserving an adequate phase margin. a rule of thumb for preserving an adequate phase margin is: cr 10 10 6 r 10 10 6 c where: c = load capacitance r = equivalent series resistance (esr) of the capacitor for example, if the load capacitor is 400 m f, then the esr of the capacitor would need to be no less than 25 m w . 25 m 10 10 6 400 f this rule of thumb assumes that all capacitors across the load are the same type and value. if different types and values are used in parallel across the load, then each individual capacitor must meet the requirements of the given equation. pcb layout guidelines it is recommended that the mc33567 be placed as physically close as possible to the external series pass mosfet transistors. use short traces to minimize extraneous signals from being magnetically or electrostatically induced on the sense or drive lines. place the sense trace and power trace in the same plane and same direction. the power trace is to be placed from the series pass transistor source lead to the load. avoid routing the sense lead near the load current return path. also avoid unterminated runs of the sense leads. if it is desired to have options where the sense lead is placed on the board, use 0 w resistor jumpers to make the alternate sense lead connection near the sense pin. nchannel mosfet selection the on semiconductor mtd3055vl nchannel mosfet was used in the characterization of the mc33567. to select a nchannel mosfet the drainsource onresistance, r ds(on) , must be considered. for best results, r ds(on) needs to be low. below is the calculation for r ds(on) . the 0.5 in the equation is to prevent saturation and to account for tolerance buildup. r ds(on) 0.5 v in v out i load where: v in = 3.3 v typically v out = 1.515 v, 1.818 v, or 2.525 v i load = current at load select a nchannel mosfet that has a r ds(on) lower than the calculated value.
mc33567 http://onsemi.com 6 drv1 sns1 shdn1 power supply drv2 sns2 shdn2 1 2 3 4 8 7 6 5 mc33567 v in sns2 shdn2 shdn1 sns1 agp card q1 q2 c4 100 m f c2 100 m f c1 100 m f c3 100 m f + 3.3 v + 12 v v in v cc figure 5. application block diagram parts list qty reference part/description vendor notes 4 c1, c2, c3, c4 100 m f electrolytic capacitor various 1 u1 mc33567 on semiconductor 2 q1, q2 mtd3055vl on semiconductor nchannel mosfet mc33567 typical characteristics figure 6. gainphase plot @ 50 m f, frequency 200 100 0 10 6 10 3 10 2 10 1 figure 7. gainphase plot @ 200 m 100 10 5 10 4 f, frequency 200 100 0 10 6 10 3 10 2 10 1 100 10 5 10 4 phase gain db phase gain db i load = 2 a c = 200 f r esr = 200 m *phase margin = 85 @ 8 khz phase margin = 48 @ 500 khz i load = 2 a c = 200 f r esr = 50 m phase margin = 48 @ 8 khz phase margin = 60 @ 200 khz
mc33567 http://onsemi.com 7 10 1.817 1.816 1.815 1.814 30 20 10 1.813 1.812 1.811 0405060 voltage (v) 8 7.8 7.4 7.6 7.2 7 6.8 1.508 1.509 1.51 1.511 1.512 1.513 1.514 1.513 1.511 1.514 1.51 1.512 1.509 1.515 6.3 10 1.822 1.828 30 1.82 1.826 40 20 10 50 t a, temperature ( c) voltage (v) 1.818 1.824 1.816 0 t a, temperature ( c) figure 8. regulator 1 load regulation vs. temperature gate drive 2 open figure 9. regulator 2 load regulation vs. temperature gate drive 1 is open voltage (v) figure 10. gate drive sink current vs. temperature t a, temperature ( c) figure 11. shdn quiescent current vs. temperature 50 ma load t a, temperature ( c) quiescent figure 12. regulator 1 line regulation vs. temperature 50 ma load (3.0 v to 3.6 v) t a, temperature ( c) figure 13. regulator 2 line regulation vs. temperature 50 ma load (3.0 v to 3.6 v) t a, temperature ( c) sink current (ma) voltage (v) 1.83 60 10 30 20 10 0405090 10 30 40 20 10 50 090 10 30 40 20 10 50 090 6.1 6.4 6 6.2 5.9 6.5 6.6 5 ma load 1.3 a load quiescent current with both shdns high regulator 2 1.814 1.812 1.81 1.508 1.507 1.506 60 70 80 70 80 90 5 ma load 1.3 a load 6.6 6.4 60 70 80 regulator 1 5.8 5.7 5.6 80 60 70 quiescent current with regulator 2 shdn high quiescent current with both shdns low 70 80 90 10 30 20 10 0 405060708090
mc33567 http://onsemi.com 8 42.5 42 41.5 41 40.5 40 39.5 39 0.9 0.88 0.86 0.84 0.82 0.8 0.78 10.8 10.75 10.7 10.65 10.6 10.55 10.5 10.45 570 560 550 540 530 520 510 500 10 8.6 8.5 30 8.4 8.3 40 20 10 50 t a, temperature ( c) voltage (v) 8.2 8.1 8 7.9 0 t a, temperature ( c) figure 14. under voltage lock out threshold vs. temperature figure 15. under voltage hysteresis vs. temperature voltage (v) figure 16. regulator 2 maximum gate voltage with shdn = 4.2 v vs. temperature v cc = 12 v t a, temperature ( c) figure 17. hiccup off time temperature t a, temperature ( c) time (ms) voltage (v) figure 18. hiccup on time vs. temperature t a, temperature ( c) time (ms) 90 series 1 60 70 80 490 480 470 10 30 40 20 10 50 090 60 70 80 10 30 40 20 10 50 090 60 70 80 10.4 10 30 40 20 10 50 090 60 70 80 regulator 2 regulator 1 10 30 40 20 10 50 090 60 70 80 regulator 2 regulator 1
mc33567 http://onsemi.com 9 ordering information device output voltage (v out1 ) regulated/bypass (v out2 ) package shipping mc33567d1 1.8 v 1.5 v/3.3 v so8 98 units/rail mc33567d1r2 1.8 v 1.5 v/3.3 v so8 2500 tape & reel mc33567d2 2.5 v 2.5 v so8 98 units/rail mc33567d2r2 2.5 v 2.5 v so8 2500 tape & reel
mc33567 http://onsemi.com 10 package dimensions so8 d suffix plastic soic package case 75107 issue v seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc33567 http://onsemi.com 11 notes
mc33567 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33567/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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